The successful application of high-K/metal gate engineering on the 45 nm technology node has made it essential and key modular engineering for technology nodes below sub-30 nm. The high-K/metal gate is divided into gate-first process and gate-last process. Since the gate-last process avoids the negative influence of ion implantation and high-temperature annealing upon the high-K/metal gate work function, currently it has become the mainstream process. At present, only Intel Corporation who pursued the high-K/gate-last route has achieved success in 45 nm and 32 nm mass production. In recent years, the giants in the industry such as Samsung, TSMC, Infineon and so on who closely follow the IBM Industry Alliance have also switched the previous development focus from the high-K/gate-first to the high-K/gate-last engineering.
The development of the chemical-mechanical planarization (CMP) process in the gate-last process integration is regarded to be the most challenging in the industry. In the conventional gate-last process, it needs the following steps: a silicon oxide isolation layer 4 and a silicon nitride isolation layer 3 on the top of polysilicon gates 2 on the substrate 1 are to ground off by the CMP process, and the grinding is not stopped until the top of the polysilicon gates 2 is exposed, the step of CMP process is called Poly opening nitride polish CMP, referred to as POP CMP for short, as shown in FIGS. 1A and 1B. Then, the polysilicon gates are removed, and the resulting trench is filled with a different metal layer 5, and then chemical-mechanical polishing is performed to the metal layer in one or more steps, the step of CMP process is the metal gate CMP, such that only the metal in the gate is left, thereby high-K/metal gate structures are ultimately obtained, as shown in FIGS. 2A and 2B.
The first POP CMP comprises a two-step CMP, one is silicon oxide CMP, and the other is silicon nitride CMP. A very high within-in-die uniformity is required for each of the two-step CMP. The control over the grinding uniformity of silicon oxide CMP process is the most critical. Due to a relatively high device density, and height differences among gates which exist before deposition of the silicon oxide layer 4, which are approximately 1000-1800 Å, the thickness differences between the silicon oxide layer on the source/drain regions and the tops of the polysilicon gates after silicon oxide deposition can reach about 1000-4000 Å or even more, as shown in FIG. 1A. As technology nodes continuously decrease in size, the conventional CMP meet with extremely high challenge in terms of improving the within-in-die uniformity for technology nodes below 45 nm. Besides innovation of the hardware configuration of the equipment used, selecting appropriate grinding slurry and grinding pad is an effective method of improving the within-in-die uniformity. Since this relates to the technical secret of respective corporations, currently there are few published documents or patent reports. If the conventional silicon oxide CMP process is employed, such great thickness differences cannot be effectively eliminated, which will be kept with the implementation of the polishing procedure until the silicon oxide polishing ends, causing large to recess to exist in the silicon oxide between polysilicon gates. Even the next step silicon nitride CMP hardly can repair it, and due to the difference in material selectivity, such silicon oxide recess may be further enlarged, as shown in FIG. 1B, the silicon oxide between gates has a first recess depth H1 which is, e.g., about 100 Å. A large recess of the silicon oxide layer 4 will directly cause a great obstacle to the metal gate CMP process, it will drastically limit the tuning range of the process. As shown in FIGS. 2A and 2B, the metal layer 5 is filled in the gate trench and meanwhile is remained in the recess of the silicon oxide layer 4 between the gates, causing a short-circuit of the device during the subsequent metal gate CMP. Likewise, as far as other features which demand for the planarization processing are concerned, such as the fin structure, the multi-gate structure, the MEMS structure and etc., they also have the similar problem, the recess of the dielectric isolation layer between the features will be kept and enlarged in the subsequent processing course, resulting in failure of the features.
Therefore, it urgently needs a method for effectively improving within-in-die uniformity directed for the POP CMP process.